UML Architecture - Revision history

Cuavas: /* Opcodes */

2025-10-03T17:59:20Z

Opcodes

← Older revision		Revision as of 19:59, 3 October 2025
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	== Opcodes ==		== Opcodes ==

	For information about particular ~~opcodes~~, see ~~one of these sections~~:		For information about particular instructions, see the documentation web site: https://docs.mamedev.org/techspecs/uml_instructions.html

	* [[UML Control Flow Opcodes]]
	* [[UML Internal Register Opcodes]]
	* [[UML Integer Opcodes]]
	* [[UML Floating Point Opcodes]]

Aaron at 20:00, 9 June 2008

2008-06-09T20:00:53Z

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Aaron: /* Integer Operations */

2008-06-09T19:39:32Z

Integer Operations

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Aaron: /* BSWAP */

2008-06-05T20:01:06Z

BSWAP

← Older revision		Revision as of 22:01, 5 June 2008
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	'''Codegen Shorthand:'''		'''Codegen Shorthand:'''
	UML_BSWAP(block, PTYPE(''dest''), PTYPE(''source'));		UML_BSWAP(block, PTYPE(''dest''), PTYPE(''source''));
	UML_BSWAP(block, PTYPE(''dest''), PTYPE(''source''));		UML_BSWAP(block, PTYPE(''dest''), PTYPE(''source''));

Aaron: /* Integer Operations */

2008-06-05T20:00:21Z

Integer Operations

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Aaron: /* ROLINS */

2008-06-04T20:30:30Z

ROLINS

← Older revision		Revision as of 22:30, 4 June 2008
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	* U — undefined		* U — undefined

	'''Description:''' The ''ROLINS'' opcode rotates the 32-bit ''source'' operand left by the number of bits specified in ''rotate'' and then inserts a subset of bits into ''dest'' under control of the ''mask''; the '''DROLINS''' opcode performs the same operation on 64-bit operands. For the 32-bit form, only the low 5 bits of ''rotate'' are considered; for the 64-bit form, only the low 6 bits of ''rotate'' are considered.		'''Description:''' The '''ROLINS''' opcode rotates the 32-bit ''source'' operand left by the number of bits specified in ''rotate'' and then inserts a subset of bits into ''dest'' under control of the ''mask''; the '''DROLINS''' opcode performs the same operation on 64-bit operands. For the 32-bit form, only the low 5 bits of ''rotate'' are considered; for the 64-bit form, only the low 6 bits of ''rotate'' are considered.

	'''Example:'''		'''Example:'''

Aaron: /* ROLAND */

2008-06-04T20:30:00Z

ROLAND

← Older revision		Revision as of 22:30, 4 June 2008
Line 1,084:		Line 1,084:
	* U — undefined		* U — undefined

	'''Description:''' The ''ROLAND'' opcode rotates the 32-bit ''source'' operand left by the number of bits specified in ''rotate'' and then ANDs the result with ''mask''; the '''DROLAND''' opcode performs the same operation on 64-bit operands. For the 32-bit form, only the low 5 bits of ''rotate'' are considered; for the 64-bit form, only the low 6 bits of ''rotate'' are considered.		'''Description:''' The '''ROLAND''' opcode rotates the 32-bit ''source'' operand left by the number of bits specified in ''rotate'' and then ANDs the result with ''mask''; the '''DROLAND''' opcode performs the same operation on 64-bit operands. For the 32-bit form, only the low 5 bits of ''rotate'' are considered; for the 64-bit form, only the low 6 bits of ''rotate'' are considered.

	'''Example:'''		'''Example:'''

Aaron: /* MULU */

2008-06-04T20:29:09Z

MULU

← Older revision		Revision as of 22:29, 4 June 2008
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	'''Description:''' The '''MULU''' opcode performs a 32-bit multiply between the ''source1'' and ''source2'' parameters and stores the lower half of the result in ''dest1'' and the upper half in ''dest2''; the '''DMULU''' opcode performs the same operation using 64-bit operands.		'''Description:''' The '''MULU''' opcode performs a 32-bit multiply between the ''source1'' and ''source2'' parameters and stores the lower half of the result in ''dest1'' and the upper half in ''dest2''; the '''DMULU''' opcode performs the same operation using 64-bit operands.

	Note that ''dest1'' can be set equal to ''dest2''; in this case, the multiply is performed and the lower half of the final result is stored to the operand specified. ~~In this case,~~ the V flag is set if the result could not be represented accurately using only the lower half, and the Z and S flags are set only based on the lower half value.		Note that ''dest1'' can be set equal to ''dest2''; in this case, the multiply is performed and only the lower half of the final result is stored to the operand specified. The flags are also set differently: the V flag is set if the result could not be represented accurately using only the lower half (normally it is undefined), and the Z and S flags are set only based on the lower half value (normally they are set based on the full double-width result).

	'''Example:'''		'''Example:'''
Line 1,300:		Line 1,300:
	{		{
	/* lower result in i0, upper result in i0 */		/* lower result in i0, upper result in i0 */
	~~UML_MULU~~(block, IREG(0), IREG(1), MEM(src1), MEM(src2));		UML_DMULU(block, IREG(0), IREG(1), MEM(src1), MEM(src2));
	}		}

Aaron: /* Integer Operations */

2008-06-04T20:24:28Z

Integer Operations

@@ Line 966: / Line 966: @@
       UML_CARRY(block, MEM(&flagsregister), IMM(CARRYBIT));
       UML_ADDC(block, IREG(0), IREG(1), IREG(2));
+  }

Aaron: /* MULU */

2008-06-04T20:20:13Z

MULU

← Older revision		Revision as of 22:20, 4 June 2008
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	** U — undefined		** U — undefined

	'''Description:''' The '''MULU''' opcode performs a 32-bit multiply between the ''source1'' and ''source2'' parameters and stores the lower half of the result in ''dest1'' and the upper half in ''dest2''; the '''~~DMULTU~~''' opcode performs the same operation using 64-bit operands.		'''Description:''' The '''MULU''' opcode performs a 32-bit multiply between the ''source1'' and ''source2'' parameters and stores the lower half of the result in ''dest1'' and the upper half in ''dest2''; the '''DMULU''' opcode performs the same operation using 64-bit operands.

	Note that ''dest1'' can be set equal to ''dest2''; in this case, the multiply is performed and the lower half of the final result is stored to the operand specified. In this case, the V flag is set if the result could not be represented accurately using only the lower half, and the Z and S flags are set only based on the lower half value.		Note that ''dest1'' can be set equal to ''dest2''; in this case, the multiply is performed and the lower half of the final result is stored to the operand specified. In this case, the V flag is set if the result could not be represented accurately using only the lower half, and the Z and S flags are set only based on the lower half value.