Address Maps

Address maps define how the address space of a CPU is layed out. This article aims to explain how memory and address space is managed in MAME.

This article is WIP.

Address Spaces

Currently, MAME supports CPUs with up to three distinct address spaces:

1. Program space (ADDRESS_SPACE_PROGRAM) is by definition the address space where all code lives. On Von Neumann architecture CPUs, it is also where data is stored. Most CPUs are Von Neumann architecture systems, and thus comingle code and data in a single address space.
2. Data space (ADDRESS_SPACE_DATA) is a separate address space where data is stored for Harvard architecture CPUs. An example of a Harvard architecture CPU in MAME is the ADSP2100.
3. I/O space (ADDRESS_SPACE_IO) is a third address space for CPUs that have separate I/O operations. For example, the Intel x86 architecture has IN and OUT instructions which are effectively reads and writes to a separate address space. In MAME, these reads and writes are directed to the I/O space.

Note that a number of CPU architectures also have internal memory that is in a separate space or domain from the other three. Memory referenced in this way is expected to be maintained internally in the CPU core and is not exposed through the memory system in MAME.

CPUs and Bus Width

Everyone has probably heard about the "8-bit" Z80 CPU or the "32-bit" 80386 CPU. But where does this notion of "8-bit" and "32-bit" come from? When referring to CPUs, there are three metrics worth considering, all of which might be used to describe a CPU, depending on which sounds better to the marketing department (seriously).

The first possible metric is the size of the internal arithmetic units in the CPU. For example, the Motorola 68000 CPU can do arithmetic operations on 32-bit numbers internally. Does this make it a 32-bit CPU? Depends on who you ask, though most people would probably say "no", because it is at odds with the other two metrics.

The second possible metric is the width of the address bus. When a CPU goes to fetch memory, it has to tell the outside world what address it wishes to access. To do this, it drives some of the pins on the chip to specify in binary the address it wants to access, and then signals a read or a write to actually cause the memory access to occur. The number of pins available on the chip for sending these addresses is referred to as the address bus width, and ultimately controls how much memory the CPU can access. For example, the original Intel 8086 has 20 address pins on it, and could access 2²⁰ bytes (or 1 MB) of memory; thus, we say it had a 20-bit address bus. When Intel created the 80286, it increased the address bus width to 24-bit (16 MB), and then to 32-bit (4 GB) with the introduction of the 80386. Which is one reason why the 80386 is called a "32-bit" CPU.

The third possible metric is the width of the data bus. This describes how many bits of data the CPU can fetch at one time. Again, this is related to pins on the chip, so a CPU that has an 8-bit data bus can fetch 8 bits (or one byte) at a time, and has 8 pins on the CPU which either send or receive the data that goes out to memory. Almost all CPUs access memory either in 8-bit, 16-bit, 32-bit, or 64-bit chunks (though there are a few oddballs that don't follow these rules). For example, the original Motorola 68000 accessed memory in 16-bit chunks, meaning it had 16 pins on the CPU which sent/received data, and thus we say it had a 16-bit data bus width. When Motorola introduced the 68020, it doubled that data bus width to 32-bits, meaning that it could fetch twice the amount of data in a single memory access. This is why the 68020 is called a "32-bit" CPU.

So why do you need to know all of this for working with address maps? Well, the first metric is irrelevant because it doesn't apply to memory accesses, but the second two metrics describe how the CPUs deal with memory, and some of those details leak into the address maps.

MAME today supports any address bus width from 1-32 bits, and it supports data bus widths of 8, 16, 32, and 64-bit. For CPUs with oddball data bus widths, we generally round up to the next highest and clean up the details in the CPU core.

Also note that each address space can have different properties, even within the same CPU. For example, the Intel 80386 has a program address space with a 32-bit address bus width, but it has an I/O address space with a 16-bit address bus width.

Address Map Structure

A typical address map looks like this (this example is taken from the qix.c driver):

static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 )
    AM_RANGE(0x8000, 0x83ff) AM_RAM AM_SHARE(1)
    AM_RANGE(0x8400, 0x87ff) AM_RAM
    AM_RANGE(0x8800, 0x8bff) AM_READNOP   /* 6850 ACIA */
    AM_RANGE(0x8c00, 0x8c00) AM_MIRROR(0x3fe) AM_READWRITE(qix_video_firq_r, qix_video_firq_w)
    AM_RANGE(0x8c01, 0x8c01) AM_MIRROR(0x3fe) AM_READWRITE(qix_data_firq_ack_r, qix_data_firq_ack_w)
    AM_RANGE(0x9000, 0x93ff) AM_READWRITE(pia_3_r, pia_3_w)
    AM_RANGE(0x9400, 0x97ff) AM_READWRITE(pia_0_r, qix_pia_0_w)
    AM_RANGE(0x9800, 0x9bff) AM_READWRITE(pia_1_r, pia_1_w)
    AM_RANGE(0x9c00, 0x9fff) AM_READWRITE(pia_2_r, pia_2_w)
    AM_RANGE(0xa000, 0xffff) AM_ROM
ADDRESS_MAP_END

As you can see, it relies heavily on macros to do the heavy lifting. In the current implementation (as of March, 2008), the macros expand into a small "constructor" function. In the future, they may just boil down to a simple data-driven tokenization. Regardless, don't worry about the actual behavior of the macros, just what they mean.

Each address map starts with an ADDRESS_MAP_START declaration. This declaration takes 3 parameters. The first parameter (main_map) is the name of the variable you are defining. Each memory map is associated with a variable name so that you can reference it in your machine configuration. The second parameter (ADDRESS_SPACE_PROGRAM) simply specifies which address space the memory map is intended for. This helps MAME ensure that you don't mix memory maps inappropriately. The final parameter (8) is the data bus width, which again is used as a cross-check against the CPU's defined data bus width for the address space you are working with.

Following the ADDRESS_MAP_START declaration is a list of address ranges. Each range starts with a begin/end address pair wrapped in an AM_RANGE macro, followed by a series of macros that describe how to handle memory accesses within that range. The details of each macro will be described in detail below.

Finally, there is an ADDRESS_MAP_END macro which ties everything up.

A few general comments about the address map above:

• First, note that this address map has everything listed in nice ascending order. This is not required, though it is usually recommended for readability.

• Second, note that there are no overlapping ranges. This is also not a requirement. Entries in the address map are always processed in reverse order, starting from the bottom and working up to the top. So any overlapping ranges which appear earlier in the list will take precedence over ranges which appear later.

Read/Write Handlers

Before diving into the details of the address map macros, let's talk about read/write handlers. The purpose of an address map is to describe what MAME should do when memory within a certain range is accessed. In its most simplistic sense, it specifies a set of functions which should be called in response to memory accesses. These are the read/write handlers.

A read handler is a function which accepts an address and perhaps a mask, and returns the value obtained by "reading" memory at that address. Here is a prototype for an 8-bit read handler:

UINT8 my_read_handler(offs_t offset);

Notice a couple of things about this definition. First, I specifically said an "8-bit" read handler, and you can see that the function returns a UINT8. This means that yes, there are 4 different handler function types, one each for 8, 16, 32, and 64-bit memory accesses. Regardless of the size of data returned, however, all the functions take an offset of type "offs_t", which today is 32 bits (though in the future we may expand it to 64). Also note that it is called an "offset", not an "address". This is because the memory system in MAME always subtracts the beginning address of a memory range from the raw address before passing it into the read/write handlers. This means that the offset parameter is always the offset relative to the starting address of the range.

Similarly, a write handler is a function which accepts an address, a value, and perhaps a mask, and "writes" memory at that address.

Address Map Macros

Below is a comprehensive list of the supported macros and what they mean.

AM_RANGE

AM_RANGE(start, end) 

The primary purpose of this macro is to declare a memory range. Any AM_* macros which follow implicitly apply to the most recently declared range. The AM_RANGE macro takes two parameters which specify an inclusive range of consecutive addresses beginning with start and ending with end (that is, an address hits in this bucket if the address >= start and address <= end).

AM_READ, AM_WRITE, AM_READWRITE

AM_READ(readhandler)
AM_WRITE(writehandler)
AM_READWRITE(readhandler, writehandler)

These macros provide pointers to functions that will be called whenever a read or write within the current range is detected. The actual prototypes and behaviors of the readhandler and writehandler functions will be described later. However, it is important to note that there is strict typechecking on the function pointers, especially in terms of data bus width, to prevent you from specifying a 16-bit readhandler in an 8-bit address map (recall that the data bus width of the address map was specified in the ADDRESS_MAP_START macro).

Instead of passing the raw address to the read/write handlers, the memory system actually passes an offset relative to the start address provided in the AM_RANGE macro. This allows for common handlers regardless of where the component is actually mapped in the address space.

In addition to regular function pointers, a small number of static identifiers are also permitted. For example, in an 8-bit address map, you can specify a readhandler of MRA8_RAM to specify a dynamically allocated region of RAM, or a writehandler of MWA8_UNMAP to specify that the current address range is unmapped for writes. More information on the supported static handler types is provided later.

The AM_READWRITE macro is really just a shortcut for AM_READ followed by AM_WRITE.

AM_MASK

AM_MASK(mask)

Specifies a bitmask which applies to the offset that is passed to the read/write handlers. By default, there is no mask, and the read/write handlers are passed in the raw address minus the start address of the current address range. If a mask is provided, this bitmask is applied in an AND operation after subtracting the start address. Thus, the value passed to the read/write handlers is really ((address - start) & mask).

AM_MIRROR

AM_MIRROR(mirror)

This macro specifies the "mirror mask" for the current address range. There are two ways to understand a mirror mask; hopefully at least one of them makes sense!

• A hardware-centric interpretation would describe a mirror mask as essentially a bitmask consisting of all bits that are ignored when the address is decoded by the hardware. Most arcade hardware does not fully decode each address; rather, in order to save on chip counts, the hardware is set up to do the minimum necessary work to separate accesses to different components in the system, and many bits are ignored. For example, in Pac-Man, bits 13 and 15 are not used at all when deciding whether an access should be directed to spriteram. Thus, the mirror mask is set as $A000.

• A software-centric interpretation would be that each bit in the mirror mask describes a "mirror" of the address range at a different address in the system. Looking again at the Pac-Man example, spriteram is traditionally thought of as existing at address $4FF0. But it turns out that you can also access it at $6FF0, $CFF0, and $EFF0, due to the fact that the hardware does not care whether bits 13 and 15 are 0 or 1. So the mirror mask of $A000 means that the memory system will replicate this address range to automatically create these mirrors by going through each bit of the mirror mask and mapping the range with that bit set to 0 and then to 1.

Note that the mirroring is by default completely hidden to the read/write handlers. This is done by making the default AM_MASK value for a mirrored range equal to the logic NOT of the mirror. In the case of Pac-Man above, for example, the mask would be ~$A000 = $5FFF. Looking at an example access to $CFF7, we would subtract the base address of $4FF0, giving an offset of $8007. Then we apply the mask of $5FFF to get the final offset of $0007.

If you want your read/write handler to see the full address with no masking, you can provide an explicit AM_MASK which will override the default value and enable you to specify which bits you wish to see.

AM_REGION

AM_REGION(region, offs)

Only useful if AM_READ/WRITE point to RAM, ROM, or BANK memory. By default, memory is allocated to back each bucket. By specifying AM_REGION, you can tell the memory system to point the base of the memory backing this bucket to a given memory 'region' at the specified 'offs'.

AM_SHARE

AM_SHARE(index)

Similar to AM_REGION, this specifies that the memory backing the current bucket is shared with other buckets. The first bucket to specify the share 'index' will use its memory as backing for all future buckets that specify AM_SHARE with the same 'index'.

AM_BASE

AM_BASE(base)

Specifies a pointer to a pointer to the base of the memory backing the current bucket.

AM_SIZE

AM_SIZE(size)

Specifies a pointer to a size_t variable which will be filled in with the size, in bytes, of the current bucket.