Midway Zeus

Midway Zeus Hardware

This topic is primarily focused on the 3D graphics hardware of the Zeus. The Zeus chip is a Midway custom 3D controller that is capable of high polygon rates. Not much is yet known about the chip, but a number of details have been reverse engineered. This page describes what is currently known/understood.

Main CPU

The main CPU driving the Zeus is -- at least in the case of Mortal Kombat 4 -- a TMS32C032 DSP running at 60 MHz.

Zeus 3D Graphics

The Zeus chip is memory mapped into the main CPU's address space at addresses from $880000-$8803FF. Keep in mind that the TMS32C032 only accesses 32-bit memory, so each of the 1,024 addresses is 32 bits wide (i.e., address $880000 references one 32-bit word, and address $880001 references a completely independent 32-bit word).

As with most external chips, the memory map for the Zeus consists of a number of registers, in this case 512 registers. One interesting aspect is that the Zeus internally appears to be a 32-bit chip, but can be accessed in (and defaults to) a 16-bit mode. The way this is done is that in 16-bit mode, accesses to odd addresses reference the upper 16 bits of a register, while accesses to even addresses reference the lower 16 bits of a register. When the chip is switched to 32-bit mode, almost all accesses are to the even registers. It is not clear what happens if you read or write to an odd address when the chip is in 32-bit mode, though the games on the hardware occasionally do so.

The 512 registers on the chip are described by their addresses. So register 0 maps to address $000, while register 1 maps to address $002, etc. This helps keep things straight when referring back to the code.

Zeus Register Map

Address	R/W	Purpose
$006	W	Low 16 bits specify texture mode
$058	W	Usually written after $05A; after writing, waits for read from $0F6 to return with bit 4 cleared
$05A	W	Usually written immediately before writing $058
$068	W	Written at startup: $00030000 = toggled on then off at startup
$080	W	Master control; configures some core chip behavior: $40000000 = set along with $02000000 when enabling FIFO empty interrupt $02000000 = enable internal data FIFO empty interrupt $01000000 = cleared along with $02000000 when disabling FIFO empty interrupt $00020000 = 16-bit (0) or 32-bit (1) mode $00000080 = set just before writing direct command to $60 $00000040 = set just before writing direct command to $60 $00000008 = cleared just before writing to offsets $200-$3FF
$084	W	$00000080 = select render page? (generally set when $CC is set to $000000 and clear when $CC is set to $800000)
$0B0	R/W	Data port for direct RAM access
$0B2	R/W	Data port for direct RAM access
$0B4	W	Address for direct RAM access $07FF0100 = mask for Y coordinate $000000FF = mask for X coordinate
$0B6	W	Direct RAM access control $80000000 = enable writes to wave RAM 0 $40000000 = enable writes to wave RAM 1 $02000000 = perform access on write to B0(0) or B2(1) ????? $00800000 = enable writes from [$B2] to depth buffer $00400000 = enable writes from [$B0] to depth buffer $00200000 = enable writes from [$B2] to RAM buffer $00100000 = enable writes from [$B0] to RAM buffer $00020000 = auto increment the address $00010000 = perform a read when the address is written $00000001 = enable direct RAM access Examples: $80A00000 when writing a single pixel (address written each time) $80A20001 when writing the right pixel of a pair (autoinc assumed) $80F60001 when writing the middle pairs of pixels (autoinc assumed) $80520001 when writing the left pixel of a pair (autoinc assumed) $82F00001 when testing wave RAM page 1 (address written each pair) $42F00001 when testing wave RAM page 0 (address written each pair) $82F60001 when uploading to wave RAM page 1 (autoinc assumed) $42F60001 when uploading to wave RAM page 0 (autoinc assumed)
$0C0	W	Written at startup = $801F2500
$0C2	W	Written at startup = $0015E591
$0C4	W	Written at startup = $000C0042 (HSYNC start/HSYNC end?)
$0C6	W	Written at startup = $0211007F (HTOTAL/HBLANK end?)
$0C8	W	Written at startup = $010300FF (VSYNC start/VBLANK start?)
$0CA	W	Written at startup = $01160107 (VTOTAL/VSYNC end?)
$0CC	W	Written at startup = $00000000 (display start address? switches to $00800000)
$0CE	W	Written at startup = $00C87620
$0E0	W	Data FIFO (see FIFO commands, below)
$0F2	R	Looped on until it returns a stable value; must change frequently; PRNG? current video line?
$0F4	R	Status register $00000800 = VBLANK? code waits for it to clear to 0 and then reset to 1 $00000140 = tested together in tight loop until both are 0 $00000008 = internal data FIFO full $00000004 = tested in tight loop along with $00000002 until at least one is set $00000002 = tested in tight loop after handling FIFO interrupt until set
$0F6	R	Status register 2 $00000010 = tested in tight loop after writing 5A/59/58 until set to 0
$200-$3FF	W	Unknown, but written in a loop with master control bit $00000008 cleared Possible fast buffer clear? One set of writes stores $7F7F to all entries. A second set writes $E00,$25,$E01,$25,...,$E7F,$25. A third set writes $52,$A0000000,...